\doxysubsubsubsection{TIM Break System }
\hypertarget{group___t_i_m___break___system}{}\label{group___t_i_m___break___system}\index{TIM Break System@{TIM Break System}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___t_i_m___break___system_ga353dd579e2ee67ce514f2bc218f64279}{TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+ECC}}~SYSCFG\+\_\+\+CFGR2\+\_\+\+ECCL
\item 
\#define \mbox{\hyperlink{group___t_i_m___break___system_ga389af93f9a1789e7de509991ef23cfec}{TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+PVD}}~SYSCFG\+\_\+\+CFGR2\+\_\+\+PVDL
\item 
\#define \mbox{\hyperlink{group___t_i_m___break___system_gaf359a8c2dde8fda9cb026926b8402dee}{TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+SRAM\+\_\+\+PARITY\+\_\+\+ERROR}}~SYSCFG\+\_\+\+CFGR2\+\_\+\+SPL
\item 
\#define \mbox{\hyperlink{group___t_i_m___break___system_ga9b84149e41633c45c50c5cdcbbd63dc0}{TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+LOCKUP}}~SYSCFG\+\_\+\+CFGR2\+\_\+\+CLL
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___t_i_m___break___system_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___t_i_m___break___system_ga353dd579e2ee67ce514f2bc218f64279}\index{TIM Break System@{TIM Break System}!TIM\_BREAK\_SYSTEM\_ECC@{TIM\_BREAK\_SYSTEM\_ECC}}
\index{TIM\_BREAK\_SYSTEM\_ECC@{TIM\_BREAK\_SYSTEM\_ECC}!TIM Break System@{TIM Break System}}
\doxysubsubsubsubsubsection{\texorpdfstring{TIM\_BREAK\_SYSTEM\_ECC}{TIM\_BREAK\_SYSTEM\_ECC}}
{\footnotesize\ttfamily \label{group___t_i_m___break___system_ga353dd579e2ee67ce514f2bc218f64279} 
\#define TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+ECC~SYSCFG\+\_\+\+CFGR2\+\_\+\+ECCL}

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 \Hypertarget{group___t_i_m___break___system_ga9b84149e41633c45c50c5cdcbbd63dc0}\index{TIM Break System@{TIM Break System}!TIM\_BREAK\_SYSTEM\_LOCKUP@{TIM\_BREAK\_SYSTEM\_LOCKUP}}
\index{TIM\_BREAK\_SYSTEM\_LOCKUP@{TIM\_BREAK\_SYSTEM\_LOCKUP}!TIM Break System@{TIM Break System}}
\doxysubsubsubsubsubsection{\texorpdfstring{TIM\_BREAK\_SYSTEM\_LOCKUP}{TIM\_BREAK\_SYSTEM\_LOCKUP}}
{\footnotesize\ttfamily \label{group___t_i_m___break___system_ga9b84149e41633c45c50c5cdcbbd63dc0} 
\#define TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+LOCKUP~SYSCFG\+\_\+\+CFGR2\+\_\+\+CLL}

Enables and locks the LOCKUP output of Cortex\+M4 with Break Input of TIM1/8/15/16/17 \Hypertarget{group___t_i_m___break___system_ga389af93f9a1789e7de509991ef23cfec}\index{TIM Break System@{TIM Break System}!TIM\_BREAK\_SYSTEM\_PVD@{TIM\_BREAK\_SYSTEM\_PVD}}
\index{TIM\_BREAK\_SYSTEM\_PVD@{TIM\_BREAK\_SYSTEM\_PVD}!TIM Break System@{TIM Break System}}
\doxysubsubsubsubsubsection{\texorpdfstring{TIM\_BREAK\_SYSTEM\_PVD}{TIM\_BREAK\_SYSTEM\_PVD}}
{\footnotesize\ttfamily \label{group___t_i_m___break___system_ga389af93f9a1789e7de509991ef23cfec} 
\#define TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+PVD~SYSCFG\+\_\+\+CFGR2\+\_\+\+PVDL}

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface \Hypertarget{group___t_i_m___break___system_gaf359a8c2dde8fda9cb026926b8402dee}\index{TIM Break System@{TIM Break System}!TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR@{TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR}}
\index{TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR@{TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR}!TIM Break System@{TIM Break System}}
\doxysubsubsubsubsubsection{\texorpdfstring{TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR}{TIM\_BREAK\_SYSTEM\_SRAM\_PARITY\_ERROR}}
{\footnotesize\ttfamily \label{group___t_i_m___break___system_gaf359a8c2dde8fda9cb026926b8402dee} 
\#define TIM\+\_\+\+BREAK\+\_\+\+SYSTEM\+\_\+\+SRAM\+\_\+\+PARITY\+\_\+\+ERROR~SYSCFG\+\_\+\+CFGR2\+\_\+\+SPL}

Enables and locks the SRAM\+\_\+\+PARITY error signal with Break Input of TIM1/8/15/16/17 